Known image processing systems such as light production presses, digital copiers and other print devices produce printed images by retrieving raw source (image) data from a scanner, processing the data through a series of transformations (i.e., image data flow), and ultimately sending the transformed data to a print engine. These operations are generally implemented by a combination of firmware and imaging architecture that include a PC processor (e.g., Intel and AMD chipsets), a memory, a communications bus and a hardware assist application specific integrated circuit (ASIC). The ASIC communicates with the PC processor through a PCI Express channel (i.e., a serial physical-layer communications protocol) located on the PC processor.
In known imaging systems, the image data flow is linear in that a single ASIC is configured to perform all data flow operations including image compression functions, color space conversions (CSC), video, traptoning, and input/output functions. An exemplary data flow for a known image processing system generally includes: (1) retrieving image data from a scanner or input/output (I/O) device; (2) performing necessary CSC; (3) compressing the data; (4) decompressing the data upon demand from the print engine; and (5) sending the data to the print engine. Consequently, the performance (i.e., speed) of the image processing system is, in part, limited by the bandwidth capabilities of the single ASIC.
Known image processing systems are further limited by architectural constraints of the PC processor that limit the image data flows (i.e., transformations in the image data) that are necessary for high speed image processing. For example, PC processors do not allow for peer to peer communication from one PCI Express channel to another. As a result, there is no way to direct memory access (DMA) data to a print engine when the engine is on a separate PCI Express channel.
Accordingly, the embodiments described hereinafter were developed in light of these and other drawbacks associated with image processing systems that employs a PC processor in communication with a single ASIC.